library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--- After multiplication by 3, we MAY HAVE 2 (instead of 1) carry bits. But it doesn't not matter
--- since, as long as there is "SOME" carry, we don't use it in the next layer.

entity div_base_4_precompute_layer is
	PORT (
	clk : in STD_LOGIC;
	denominator : in STD_LOGIC_VECTOR(31 downto 0);
	
	out3_main : out STD_LOGIC_VECTOR(31 downto 0);
	out3_overflow : out STD_LOGIC
	);
end div_base_4_precompute_layer;

architecture Behavioral of div_base_4_precompute_layer is
	component Adder_32x32 is
	Port (carry_in			: in	STD_LOGIC;							  	--- '1' if we want a carry into the adder
			Arg1				: in	STD_LOGIC_VECTOR (31 downto 0); 	--- Input for additon
			Arg2				: in	STD_LOGIC_VECTOR (31 downto 0); 	--- Input for addition
			Result			: out	STD_LOGIC_VECTOR (31 downto 0); 	--- Main 32 bits of results
			carry_out		: out	STD_LOGIC								--- 
			);
	end component;
	
	signal adder_carry_out : STD_LOGIC;
	signal adder_result : STD_LOGIC_VECTOR (31 downto 0);
begin

	preprocess_adder : Adder_32x32
	PORT MAP(
	carry_in => '0',
	arg1 => denominator,
	arg2(31 downto 1) => denominator(30 downto 0),
	arg2(0) => '0',
	carry_out => adder_carry_out,
	result => adder_result);
	
	process(clk)
	begin
		if (clk'event and clk='1') then
			out3_main <= adder_result;
			out3_overflow <= denominator(31) or adder_carry_out;
		end if;
	end process;

end Behavioral;

